Categories: Electrical Engineering

High-voltage pulse-triggered SR latch level-shifter design considerations

Dennis Oland Larsen, Pere Llimos Muntal, Ivan H. H. Jorgensen, Erik Bruun

DOI: 10.1109/norchip.2014.7004737

Proceedings-article published October 2014 in 2014 NORCHIP
© IEEE

Keywords: #ic-design  #level-shifting  #integrated circuit  Edit keywords

2 1 4.0 Posted: 10.Mar.2018

Impressive results are shown by simulations and IC-fabrication. The authors initially design a SR-pulse-triggered level-shifter for high voltage application and test it in the lab giving great results. This implementation is furthermore improved upon vastly by minimizing chip area, power consumption and propagation delay. The authors consider process corners and start-up conditions taking the reader well through the proces of level-shifter design on chip.

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The improved version of the pulse-triggered SR latch leaves a lot of calculations to be done regarding W/L ratios, DC currents and the like. It could easily have been included to increase readability and application.

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